Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6343345
Kind Code:
A
Abstract:

PURPOSE: To obtain optimum output time characteristics by using an output transistor, size of which is varied, and setting the output impedance of an output terminal in response to load.

CONSTITUTION: An LSI such as a 2 input AND circuit is formed by P channel and N channel output transistors T1, T2, etc. functioning as a 2 input NAND circuit and an inverter circuit. The width WP and WN of these transistors T1, T2 is altered, load by a standard cell and a wiring is calculated after the arrangement and wiring of the standard cell, and width WP and WN is selected in response to load, thus optimally setting the output impedance of output terminals OUT. Accordingly, optimum output time characteristics are obtained, thus improving the degree of freedom of a design.


Inventors:
TAKAGI YOSHIYUKI
Application Number:
JP18711486A
Publication Date:
February 24, 1988
Filing Date:
August 08, 1986
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/8234; H01L21/82; H01L27/02; H01L27/088; (IPC1-7): H01L21/82; H01L27/08
Attorney, Agent or Firm:
Toshio Nakao