Title:
集積回路および液晶表示デバイス
Document Type and Number:
Japanese Patent JP4237288
Kind Code:
B2
Abstract:
The signal input of the toggle (63) is connected to the module signal input and the clock input (clk) is connected to the module clock input. In order to provide at its outlet, using the input signal and the clock signal, a signal identical to the input signal but synchronised with the clock signal, the module (6) has a second toggle (65) of the D type, of which the clock input is connected to that of the first toggle via an inverter (61) and of which the output is connected to the module output. The output of the first toggle is connected to the data signal input of the second toggle via a multiplexer (64), controlled by a digital command signal containing information on the phase relationship between the data signal at the input and the clock signal, so as to apply to the second toggle either the input data signal or the signal coming from the first toggle.
Inventors:
Peter Forenkamp
Herve Mari
Herve Mari
Application Number:
JP8403498A
Publication Date:
March 11, 2009
Filing Date:
March 30, 1998
Export Citation:
Assignee:
NXP B.V.
International Classes:
G02F1/133; H04L7/02; G06F1/08; G06F1/12; G09G3/20; G09G3/36; H03L7/00
Foreign References:
| US5220581 | ||||
| US5245637 | ||||
| EP0716501A1 |
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Tatsuya Sawada