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Title:
INTEGRATED COMPARATOR CIRCUIT
Document Type and Number:
Japanese Patent JPH07191065
Kind Code:
A
Abstract:

PURPOSE: To provide an integrated comparator circuit which can be manufactured by an N-MOS or P-MOS technique simpler than a C-MOS technique.

CONSTITUTION: An integrated comparator circuit has a series circuit consisting of first and second MOSFET 1, 2 connected between a first terminal 5 and first input terminal 8 for operational voltage, an inverter stage having third and fourth MOSFET 3, 4 connected between third and fourth terminals for the operational voltage and a connection between a nodal point 10 between the first MOSFET 1 and the second MOSFET 2 on one hand and a gate terminal of the fourth MOSFET 4 on the other hand. In the integrated comparator circuit, the transmission characteristic curve of the second MOSFET 4 is steeper than that of the fourth MOSFET 4, the second and fourth MOSFET 1, 4 are an enhancement type MOSFET, the first and third MOSFET 1, 3 are a depression type MOSFET and all MOSFETs are of equal channel form.


Inventors:
HORUGAA HAIRU
YOOZEFUUMACHIASU GANCHIORAA
RAINARUTO ZANDAA
Application Number:
JP28448994A
Publication Date:
July 28, 1995
Filing Date:
October 24, 1994
Export Citation:
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Assignee:
SIEMENS AG
International Classes:
G01R19/165; H03F3/345; H03K5/02; H03K5/08; H03K17/30; (IPC1-7): G01R19/165; H03K5/08
Attorney, Agent or Firm:
Tomimura Kiyoshi



 
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