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Patent Searching and Data


Title:
INTEGRATED LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH0575064
Kind Code:
A
Abstract:

PURPOSE: To prevent erroneous operation due to noise entered through an input pin in a memory where a current consumption is lowered by decreasing the power supply voltage during standby (data retaining state).

CONSTITUTION: A signal transmission gate is interlaid between an input pin and an input buffer, means for detecting the drop in internal power supply voltage is provided, and the gate is turned off during drop in power supply voltage, thereby inhibiting the transmission of signals from the input pin to the input buffer. By doing this, even though the logic threshold voltage of the input buffer is dropped as a result of a decrease in the internal power supply voltage, the gate interlaid between the input pin and the input buffer is turned off, and noise entered into the input pin cannot be transmitted to the input buffer so that erroneous operation of the circuit can be prevented.


Inventors:
MIMURA AKIMITSU
KAJITANI KAZUHIKO
YAMAZAKI TAKASHI
Application Number:
JP26110091A
Publication Date:
March 26, 1993
Filing Date:
September 11, 1991
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/10; G11C11/403; G11C11/407; G11C11/409; H01L21/8242; H01L27/108; H03K19/00; (IPC1-7): H01L27/108
Attorney, Agent or Firm:
Tomio Ohinata