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Title:
INTEGRATED LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS5915330
Kind Code:
A
Abstract:

PURPOSE: To reduce greatly the ON/OFF current, by giving a shift of timing between an OFF action of a transistor of an output stage and the start of an OFF buffer circuit.

CONSTITUTION: When inputs (i) and (j) are set at a high level with transistors TRQ6 and Q8 turned on respectively, a TRQ11 is also turned on and a current (i) flows. Therefore, it is possible to lower the potential of a point (m) until an OFF buffer circuit D is turned off by selecting a proper ratio between resistances R9 and R10. Under such conditions, if the input (i) or (j) is changed to a low level, a TRQ7 is turned off and the potential rises up at a point (l). However, the circuit D is kept off since the potential of a point (n) is lowered by a resistance R9i less than VCC while the TRQ11 is kept on. THen the TRQ11 is turned off only when the TRQ8 is turned off. Thus the potential rises up at the point (n) to turn on the circuit D. As a result, a simultaneous ON state never virtually exists for both TRQ8 and circuit D. This circuit reduces greatly the ON/OFF current.


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Inventors:
ASOU AKIRA
Application Number:
JP12388482A
Publication Date:
January 26, 1984
Filing Date:
July 16, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/088; H03K19/00; (IPC1-7): H03K19/088
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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