Title:
INTEGRATED POWER SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0831945
Kind Code:
A
Abstract:
PURPOSE: To prevent the occurrence of a parasitic structure between a driving circuit and a function block, by arranging a third area of a second conductivity type between a first region and a second region and setting the potential of the third region to be different from that of the first region. CONSTITUTION: A third region 21 is p-doped in the same way as a first region 15 and a second region 16. It is desirable that it has the same depth. The third region 21 has a contact part having potential different from that of the first region 15. When MOSFET 1 is switched to an interruption state from a conductive state, a parasitic transistor is generated between the first region 15 and the third region 21. The potential change of the region 21, which is generated at the same time as the supply of a parasitic transistor 23, is not important for the function of an integrated semiconductor device, because the potential of the region 16 is not changed. When the third region 21 circularly surrounds the second region 16, the formation of a parasitic transistor 22 is securely prevented.
Inventors:
GANTIOLER JOSEF-MATTHIAS (DE)
SANDER RAINALD (DE)
LEIPOLD LUDWIG (DE)
STENGL JENS-PETER (DE)
TIHANYI JENOE (DE)
SANDER RAINALD (DE)
LEIPOLD LUDWIG (DE)
STENGL JENS-PETER (DE)
TIHANYI JENOE (DE)
Application Number:
JP18821595A
Publication Date:
February 02, 1996
Filing Date:
June 30, 1995
Export Citation:
Assignee:
SIEMENS AG (DE)
International Classes:
H01L27/04; H01L21/822; H01L21/8234; H01L27/02; H01L27/088; (IPC1-7): H01L21/8234; H01L21/822; H01L27/04; H01L27/088
Attorney, Agent or Firm:
Tomimura Kiyoshi
Next Patent: SEMICONDUCTOR MANUFACTURING METHOD