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Patent Searching and Data


Title:
INTEGRATING CIRCUIT
Document Type and Number:
Japanese Patent JPH04215127
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of elements and the power consumption of a one-bit input integrating circuit.

CONSTITUTION: The data input of a 2N-bit shift register 2 having two initializing inputs is connected to a positive power source VDD, and the output is connected to an inverter circuit 3 and the clock input of an initializable M-bit register 4, and the output of the circuit 3 is connected to an initializing input R1 of the register 2, and the output of an M-bit adder 5 is connected to an input D of the register 4, and the output of the register 4 is connected to the input of the adder 5 and an output terminal 6, and a data input 9 and a clock signal 7 are connected to the inputs of a two-input AND circuit 8, and the output of the circuit 8 is connected to the clock input of the register 2, and outputs of D type flip flops 1 of the register 2 are connected to a 2N-bit output terminal 10, and an external initializing terminal 11 is connected to initializing inputs of registers 2 and 4.


Inventors:
KANO TOSHIYUKI
Application Number:
JP41035990A
Publication Date:
August 05, 1992
Filing Date:
December 13, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F7/62; (IPC1-7): G06F7/62
Attorney, Agent or Firm:
Naotaka Ide