Title:
半導体層の上のグラフェン及びボロン窒化物ヘテロ構造デバイスの統合
Document Type and Number:
Japanese Patent JP7293258
Kind Code:
B2
Abstract:
A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.
Inventors:
Archana Venugopal
Luigi Colombo
Arup Polly
Luigi Colombo
Arup Polly
Application Number:
JP2020568951A
Publication Date:
June 19, 2023
Filing Date:
March 04, 2019
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L29/786; H01L21/336
Domestic Patent References:
| JP2020508587A | ||||
| JP2017225100A |
Foreign References:
| US20170032977 |
Attorney, Agent or Firm:
Hitoshi Sato
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