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Title:
INTER-CPU INTERFACE CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH03286246
Kind Code:
A
Abstract:

PURPOSE: To make the change of the program of a sub-CPU part unnecessary for the change and the addition of the function of a command by selecting optionally the executing order of a basic operation module located in the sub- CPU part from a main CPU part.

CONSTITUTION: The main CPU part 3 sets the address of a memory address to the input/output data register 42 of the input/output port part 4 of the sub- CPU part 8 through an input/output data register 22 in the input/output port part 2. It sets the starting address of the basic operation module to the register 41 of the sub-CPU part 8 through the register 21. Because the address was set to the starting address register 41, a control part 52 in a program control part 5 sets the starting address of the basic operation module to a counter 51, and makes a program executing part 6 execute the program. Similarly, the memory contents of the set address set beforehand are read out by the program executing part 6, and are set to the input/output data register 22 of the input/output port 2 of the CPU 3 through the input/output data register 42. Similarly, by changing the executing order of the basic operation module, write-in to the memory of the sub-CPU part 8 and read-out from an internal register are executed.


Inventors:
OMIYA MOTOHIKO
KOIZUMI SHIGERU
Application Number:
JP8670590A
Publication Date:
December 17, 1991
Filing Date:
March 31, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F15/16; G06F9/06; G06F15/17; (IPC1-7): G06F9/06; G06F15/16
Domestic Patent References:
JPS62293372A1987-12-19
Attorney, Agent or Firm:
Yutaro Kumagai