PURPOSE: To transfer data between memories directly at a high speed by making an address counter operatable and counting up it with a clock signal while a CPU releases a bus.

CONSTITUTION: Though a gate 6 is normally turned on, it is turned off by a transfer control signal C in the high-speed data transfer mode to disconnect a CPU 4 from a system address bus SAB. A gate 7 has a read gate and a write gate, and they are turned off together by the control signal C in the high-speed data transfer mode to disconnect the CPU 4 from a system data bus SDB. An address counter control part 5 has an address counter, and this counter is made unoperated normally; but in the high speed data transfer mode (the CPU released the bus SAB), the counter is made operatable and is counted up by every clock signal from a clock generating part 3 and the address as the output is outputted onto the bus SAB.