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Patent Searching and Data


Title:
INTER-PROCESSOR COMMUNICATION RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JPH03231351
Kind Code:
A
Abstract:

PURPOSE: To shorten the waiting time for confirmation of answers to the communication requests received from all processors by detecting the answers returned from all processors connected logically to each other based on the answer information and the connection information and then producing an interruption to the working processing.

CONSTITUTION: Four processors are logically connected to each other, and the communication requests are given to all processors when the processor No. of its own device is equal to 0. Then an instruction expecting an answer of the end of the preceding processing is carried out by a processor of No.0. Finally an answer is returned from a processor of No.2. That is, the contents of an answer register 3 are equal to 0111 when the answers are returned from all processors. Furthermore 1000 is stored in a processor No. register 4 since the processor No. of its own device is equal to 0. An OR is applied for each bit of both registers 3 and 4, and 1 is outputted from OR gates 5 - 8 respectively. Then an answer end instruction 107 is outputted from an AND gate 9 and then set to an answer and register 10 as 1. Thus an interruption is produced to the firmware.


Inventors:
TAKATO MASAHIKO
Application Number:
JP2790290A
Publication Date:
October 15, 1991
Filing Date:
February 07, 1990
Export Citation:
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Assignee:
KOFU NIPPON DENKI KK
International Classes:
G06F15/16; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Yanagi Shin Kawai