Title:
INTER-PROCESSOR INFORMATION TRANSFER SYSTEM
Document Type and Number:
Japanese Patent JPS6441058
Kind Code:
A
Abstract:
PURPOSE:To enable a processing part to carry out a process in parallel with another process by setting an idle receiving state regardless of the working state of the processing part and in case the processing part has its processing margin. CONSTITUTION:A processing part 30 informs an idle state to a receiving state setting means 23 during execution of a certain process and in case the part 30 itself has its processing margin and gives a command to a state information transmitting means 24 to transmit the idle receiving state to the transmitter side. The information is received by an information receiving means 21 from the transmitter side according to the transmission of said idle state and then stored in a processing information storing means 22. Based on this information, the part 30 accepts a processing item and processes it in the previous procedure. When the part 30 has no processing margin, the part 30 informs a busy receiving state to the means 23 and returns to the previous procedure to process the accepted item. Thus a processor can process plural processes in parallel with each other via the processing part.
Inventors:
SHINYA MASAJI
Application Number:
JP19749387A
Publication Date:
February 13, 1989
Filing Date:
August 06, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F13/38; G06F15/16; G06F15/177; (IPC1-7): G06F13/38; G06F15/16
Attorney, Agent or Firm:
Uchihara Shin