Title:
INTERFACE CIRCUIT FOR SERIAL D/A CONVERTER
Document Type and Number:
Japanese Patent JP3394159
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To adjust an output bit width while suppressing a circuit scale of the interface circuit for a serial D/A converter.
SOLUTION: This circuit is provided with a phase modulator 24 that controls a phase of a control signal (word clock WCLK and LR clock LRCK) received by the serial D/A converter depending on a setting value in a bit width designation register 28 to adjust a bit number of one of input data received by the serial D/A converter by not shifting parallel data from a signal processing system but controlling the phase of the control signal. Thus, an output bit width of the interface circuit is substantially adjusted depending on a value of a bit width designation register.
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Inventors:
Takashi Maki
Application Number:
JP17158797A
Publication Date:
April 07, 2003
Filing Date:
June 27, 1997
Export Citation:
Assignee:
株式会社リコー
International Classes:
G11B20/10; G11B20/14; H03M1/82; H03M9/00; (IPC1-7): H03M1/82; G11B20/10; G11B20/14
Domestic Patent References:
| JP66240A | ||||
| JP559979U |
Attorney, Agent or Firm:
Aoyama Ryo (2 outside people)