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Title:
INTERFACE SYSTEM OF SIGNAL PROCESSOR AND CONTROLLER
Document Type and Number:
Japanese Patent JPH10254824
Kind Code:
A
Abstract:

To accelerate and simplify an interface of DSP (signal processor) and a controller.

The memory space of DSP 10 and the controller 30 is made a unified specification with respect to a buffer memory 20 to use the interface between with the memory 20 for an interface between with the controller 30 in common. Thereby the interface of the memory 20 and the controller 30 are made common to simplify and accelerate by a parallel interface is realized. In addition when the memory 20 is DRAM, the interface of DSP10 and the controller 30 is executed during its refreshing cycle.


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Inventors:
JIBIKI TADASHI
ZEN HIDEMORI
KIMURA YASUNARI
Application Number:
JP5217697A
Publication Date:
September 25, 1998
Filing Date:
March 07, 1997
Export Citation:
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Assignee:
NIPPON SAMUSUN KK
International Classes:
G06F13/38; G06F13/00; (IPC1-7): G06F13/38; G06F13/00
Attorney, Agent or Firm:
Takeshi Takatsuki



 
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