PURPOSE: To obviate an exclusive external bus type mode signal line connected to a CPU by providing a means which detects the presence of an address latch enable signal to a conventional input/output interface that can correspond to two types of CPU.

CONSTITUTION: In case an input/output interface 20 is used as an input/output port of a multiplex CPU, an address latch enable signal ALE C is detected by a flip-flop circuit 21. The circuit 21 supplies continuously a level signal B indicating a multiplex bus type to a type indicating signal terminal 3-1. While the signal ALE C is not delivered from the CPU as long as a non-multiplex CPU is connected to a read/write control circuit 10. Therefore a level signal '0' is supplied to the terminal 3-1 from the circuit 21. As a result, an address control circuit 9 can select an internal bus in response to the type of the CPU.