PURPOSE: To attain an easy and high speed memory access by providing respectively an ECC circuit (error detecting correcting circuit of data) and a part writing circuit at a memory formed at plural banks.
CONSTITUTION: Respective banks 11-1, 11-2...11-n of a device are formed by memories 10-1, 10-2...10-n in which the reading and writing of the data are executed through the common terminal. At the banks 11-1W11-2...11-n, ECC circuits 12-1, 12-2...12-n and part writing circuits 13-1, 13-2...13-n are respectively provided. Thus, the access for the banks 11-1, 11-2...11-n can be independently separately executed. Namely, since the ECC circuit and the part writing circuit are provided at respective banks formed by the memory in which the reading and writing of the data are executed through a common terminal. The memory increase in accordance with the request of a user can be executed, the power consumption is minimized, the access control is facilitated and a high speed access can be executed.
SUDO KIYOSHI
KANEKO TADASHI
| JPS54109333A | 1979-08-27 |