Title:
INTERLOCK PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JP3825919
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To guarantee that all of multiplexed processing circuits are normally operated and an original function by multiplex is achieved.
SOLUTION: This circuit is provided with plural abnormality detection circuits 22 and 32 for respectively independently detecting a certain specified abnormal state, lock signal output circuits 41 and 42 for outputting prescribed lock signals in the case that at least one of the abnormality detection circuits detect the abnormal state and release signal output circuits 23, 33, 24, 34, 40 and 41 for outputting release signals for indicating that the lock signals are released only when, in the case that a prescribed release signal is inputted after the lock signal is outputted, all the abnormality detection circuits detect the abnormal state when the lock signals are outputted. Or, instead of the release signal output circuits, an alarm signal output circuit for outputting prescribed alarm signals when one of the abnormality detection circuits does not detect the abnormal state when the lock signals are outputted is provided.
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Inventors:
Mitsuya Sato
Application Number:
JP16583198A
Publication Date:
September 27, 2006
Filing Date:
June 01, 1998
Export Citation:
Assignee:
Canon Inc
International Classes:
G05B9/02; H01L21/677; B25J9/16; F16P3/08; G05B9/03; (IPC1-7): G05B9/02; G05B9/03; //H01L21/68
Domestic Patent References:
| JP7122162A | ||||
| JP4052701A |
Attorney, Agent or Firm:
Tetsuya Ito
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