INTERNAL CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME

Japanese Patent JP3847961

B2

PROBLEM TO BE SOLVED: To provide an internal clock signal generator in which a delay-locked loop DLL or a phase-locked loop PLL is coupled with a synchronization delay circuit, and synchronization is locked at high speed with high accuracy and to provide the semiconductor memory device with the internal clock signal generator.
SOLUTION: A phase-locked loop PLL 202 or a delay-locked loop DLL is coupled with a synchronization delay circuit 201 such as an SDL. The synchronization delay circuit 201 generates a clock signal which is roughly synchronized with an external clock signal. The phase-locked loop PLL 202 or a delay-locked loop DLL generates an internal clock signal, accurately synchronized with an external clock signal based on the clock signal outputted from the synchronization delay circuit 201. Thus, the internal clock signal is phase-locked quickly to the external clock signal, thereby advantageously increasing the accuracy of locking range.

Lee Sadafumi

JP18776998A

November 22, 2006

July 02, 1998

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Samsung Electronics Co.,Ltd.

G11C11/407; G06F1/10; H03L7/08; H03K5/135; H03L7/00; H03L7/081; H03L7/087; H03L7/099; (IPC1-7): H03L7/08; G11C11/407

JP9034584A
JP8191245A
JP9186584A

Yasunori Otsuka
Kenichi Matsumoto

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