To provide the interpolation digital filter which eliminates the need to use a phase-locked loop and is low-cost by making it possible to operate with a master clock of low frequency such as 256 Hz.

This filter operates at the frequency of the master clock of 256 Hz and generates a 32-bit parallel interpolation data signal of 8 Fs in sampling frequency by alternately switching 32-bit parallel interpolating data signals of 4 Fs in sampling frequency outputted from a couple of series/parallel converters 36 and 38. When a 32-bit input parallel data signal DIN which is sampled at 1 Fs is converted to a 32-bit output parallel data signal DOUT sampled at 8 Fs by using the digital filter, the master clock of the low frequency can be used as it is and the phase-locked loop is not necessary, thereby saving the manufacturing cost.