Title:
INTERRUPTABLE VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP USING THE SAME
Document Type and Number:
Japanese Patent JP2813866
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a phase-locked loop(PLL) including an ECL gate stage having controlled falling time.
SOLUTION: The fall-time of an ECL gate is exactly controlled while using a capacitor connected between a positive power source and the output of the ECL gate and using a variable current source connected between the ground and the output of the ECL gate. By connecting three ECL gates in the ring configuration, a VCO 132 is provided and by applying a non-inverted input to one ECL gate, the VCO 132 can be interrupted. By combining this VCO 132 with a phase detector, the PLL can be provided.
Inventors:
David El Chambell
Application Number:
JP25100095A
Publication Date:
October 22, 1998
Filing Date:
September 28, 1995
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
H03B5/02; G01R29/02; H03K3/03; H03K3/282; H03K3/70; H03K9/06; H03K19/086; H03L7/07; H03L7/08; H03L7/099; H03M5/12; H04L25/49; H03K5/00; (IPC1-7): H03L7/099; G01R29/02; H03K3/282; H03K19/086; H03L7/08; H03M5/12; H04L25/49
Domestic Patent References:
| JP5783922A | ||||
| JP53124956A | ||||
| JP4932577A | ||||
| JP55621A | ||||
| JP5334948U | ||||
| JP52157745U |
Foreign References:
| US3431505A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)