PURPOSE: To attain versatile interruption processings by identifying a general interruption and a specific interruption and holding the state so far and a specific interruption generating address when the specific interruption is generated to allow the instruction to reference the hold information.

CONSTITUTION: A storage device 1 having a memory 2 and a memory control circuit 3 is provided at the inside or outside of a processor of an interruption control system and an interruption control circuit 4 is connected to the device 1. Further, a specific interruption designating latch 5 is connected to the circuit 4 and a common bus 18 at the inside of the processor is connected to the circuit 4 and the latch 5. Further, the device 1 is connected to the common bus 18 via a main address latch 20 and a data latch 9 or the like. Further, the general interruption and the specific interruption are identified by the circuit 4, and when the specific interruption is generated, the state before the generation and the specific interruption generation address are stored in the latch 5. The hold information is referenced by an instruction to attain versatile interruption to each device connected to the common bus.