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Patent Searching and Data


Title:
INTERRUPTION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH03127128
Kind Code:
A
Abstract:

PURPOSE: To decrease the processing time controlled by a multi-OS control program by controlling an interruption control flag operating instruction operated on a multi-OS system by the multi-OS control program only in the case of a specific condition.

CONSTITUTION: In the case a guest OS 1 can execute an interruption processing, an interruption control program 4 executes a notice of an interruption to a CPU 5 and allows the guest OS 1 to execute the interruption processing. In the case the guest OS 1 is inhibiting the execution of the interruption processing, the interruption control program 4 switches an interruption control flag operating switch 2 to the side for executing a notice to the interruption control program 4 and checks an interruption control flag operating instruction issued by the guest OS 1. At the time when the guest OS 1 issues the interruption control flag operating instruction for setting an interruption control flag to a state that the interruption processing can be executed, the interruption control program 4 executes a notice of an interruption to the CPU 5 and allows the guest OS 1 to execute the interruption processing, and simultaneously, switches the interruption control flag 6 of the CPU. In such a way, the control processing time of the multi-OS control program can be reduced.


Inventors:
MITSUOKA SEIJI
WATANABE KAZUHISA
Application Number:
JP26706789A
Publication Date:
May 30, 1991
Filing Date:
October 12, 1989
Export Citation:
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Assignee:
NEC CORP
NEC SOFTWARE LTD
International Classes:
G06F9/48; G06F9/46; (IPC1-7): G06F9/46
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)