PURPOSE: To use only one binary counter and interruption address bus each for interruption processing, by latching the address of an interruption signal when an interruption control part receives the interruption signal, and informing a processor of the address.

CONSTITUTION: If the interruption of a request for processing is caused on an I/02, an interruption signal is outputted to an interruption signal line IS2 when its address coincides with the address on an interruption address bus IAB. This interruption signal is set in the interruption pulse detection part DET2 of the interruption control part ICN, whose output is used as memory pulses of a register RG2 and also inputted to a processor PRO. Consequently, the address of the I/02 is set in the RG2. Then, the PRO sends out the address of the I/02 to an address bus AB. At this time, a coincidence detection part A2 detects the address coincidence between the RG2 and AB, so the DET2 is reset. Further, the I/02 when receiving the address signal from the AB resets the interruption request generated so far.