PURPOSE: To delete a tag memory without increasing the frequency of invalidation processing by providing a register provided with a storage part for storing invalidated block numbers and a comparator which compares the block numbers with addresses of writing to a main storage, and a register.
CONSTITUTION: For example, a block number in the storage part of the register 15 coincides with the address of writing to the main storage 12 when a DMA controller 13 on a system bus 3 writes data in the main storage 12. At this time, an invalidation processing request signal 8 is sent from the register 15 to a control part 6, generates a bus release request signal 10 to stop a processor 1 temporarily. Then the bits of the corresponding block on the cache memory 2 are reset and a new block number is stored in the storage part of the register 15 at the same time. If the address does not coincide, the register 15 does not generate the invalidation processing request signal 8. Therefore, no matter how many times the controller 13 writes data in the same block, the invalidation processing is performed when the data is written only once, but the writing is not performed in other cases.
| JP2003076609 | MEMORY ACCESS DEVICE AND ITS METHOD |
| WO/2009/001153 | MEMORY PROTECTION UNIT IN A VIRTUAL PROCESSING ENVIRONMENT |
| JPS63121948 | INFORMATION PROCESSOR |
HATASHITA TOYOHITO
ISHIDA HITOSHI
