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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH07106875
Kind Code:
A
Abstract:

PURPOSE: To make an output voltage amplitude of a GaAs FET differential amplifier using a resistance load constant against temperature fluctuation by comparing a gate bias voltage with a comparison reference voltage by a voltage comparator.

CONSTITUTION: When a temperature is fluctuated resulting in decreasing an output voltage Vb of a bias circuit than a comparison reference voltage Vr, since an output voltage Vao of a voltage comparator 8 decreases, a gate-source voltage Vgs of an n-channel GaAs FET4 decreases and the output voltage Vb of the bias circuit is equal to the comparison reference voltage Vr. On the other hand, when the output voltage Vb is larger than the comparison reference voltage Vr, since the output voltage Vao of the voltage comparator 8 increases, the voltage Vgs of the FET 4 increases and the output voltage Vb decreases and is equal to the comparison reference voltage Vr. Since the gate-source voltage Vgs of the FET 4 is controlled so as to make the output voltage Vb equal to the comparison reference voltage Vr in this way against temperature fluctuation, a gate electrode of a constant current source 3 connected in common to a gate electrode of the n-channel GaAs FET4 is simultaneously controlled thereby suppressing the fluctuation of the amplitude of output voltage.


Inventors:
OE SHINICHI
Application Number:
JP24418093A
Publication Date:
April 21, 1995
Filing Date:
September 30, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03F1/34; H03F3/45; (IPC1-7): H03F3/45; H03F1/34
Domestic Patent References:
JP59067018B
JPH05252020A1993-09-28
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)