PURPOSE: To decrease the delay of a time constant comprising an input protection resistor and a gate capacitor by connecting two transistors (TRs) in cascade to a TR to which an external input signal is inputted to reduce the gate capacitance.

CONSTITUTION: When an external input signal goes from high to low level, a TRQ isturned off, a node N rises from a low to high level, a gate level of the TRQ reaches a power supply voltage V or over by the coupling of the capacitive element C and the node N remains a high level up to the V. The TRQ to the gate of which the node N being a high level by the coupling of the C is connected is turned on and the 1st stage output signal goes to a high level. Thus, since the load of the node N being the drain of the TRQ consists of only the gate capacitance of the TRQ, the size of the TRQ is made very small and a small gate capacitance is usable.