Title:
ION IMPLANTATION
Document Type and Number:
Japanese Patent JP3211865
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To maintain the optimum implantation conditions for a gate electrode edge and suppress channeling in a substrate by tilting the ion implantation direction at an angle within a specified range from the vertical direction to the substrate and permitting the tilting direction to be at an angle within a specified range from (011) direction or (0T1) direction.
SOLUTION: The optimum implantation angle to a substrate (angle between a direction vertical to the substrate and an ion implantation direction) is selected within a range of 7-60°, in response to the transistor characteristics. Then, an angle &phiv between the component parallel to the wafer surface in the ion implantation directions 8 and 8' and a direction (011) is permitted to be within a range of 5-20°, the same angle &phiv is applied to the ion implantation directions 8 and 8', implantation directions such as 8 and 8' are selected for both edges at least in two types of gate directions, and uniformity for all gate edges is obtained. Thus, the performance of a MOS transistor, considering the gate electrode direction and suppression of channeling in the substrate are both optimized.
Inventors:
Hiroshi Kitajima
Application Number:
JP13836396A
Publication Date:
September 25, 2001
Filing Date:
May 31, 1996
Export Citation:
Assignee:
NEC
International Classes:
C23C14/48; H01L21/265; H01L21/336; H01L29/78; (IPC1-7): H01L21/265; C23C14/48; H01L29/78
Domestic Patent References:
| JP63274767A | ||||
| JP6291074A | ||||
| JP6260496A | ||||
| JP63233567A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)