PURPOSE: To attain stable operation of the circuit against power noise by comparing outputs of inverters with a different logical threshold level so as to detect power noise thereby adjusting the logic threshold level of the inverters.

CONSTITUTION: A 1st detection means 110 outputs a high level when a common level SS is a 1st prescribed value or over or a power voltage CC is a 2nd prescribed level or below, and outputs a low level when the common level is decreased or the power voltage is increased. A 2nd detection means 120 outputs a low level when the common level SS is a 1st prescribed value or below or the power voltage CC is a 2nd prescribed level or over, and outputs a high level when the common level rises or the power voltage is decreased. A 2nd one conduction enhancement transistor (TR) QP1 receives an output of the 1st detection means 110 to its gate and a 2nd other conduction enhancement TR QN7 receives an output of the 2nd detection means 120 to its gate to prevent fluctuation of the logic threshold level against power noise. Thus, the circuit acts stably against power noise.