Title:
ISOLATOR AND METHOD FOR MANUFACTURING ISOLATOR
Document Type and Number:
Japanese Patent JP2023131665
Kind Code:
A
Abstract:
To provide an isolator that reduces the impact of YIG in a semiconductor process, and a method for manufacturing the isolator.SOLUTION: An isolator 10 comprises: a substrate 50 that has a substrate surface 50A; waveguides 21, 22 that are located on the substrate surface 50A and have first surfaces 211, 221 that face the substrate surface 50A, second surfaces 212, 222 that are reverse thereto, and side surfaces 213, 223; a groove 30 that has a bottom part and a side part where at least some of the side surfaces 213, 223 of the waveguides 21, 22 is exposed; a mask 40 that is located overlapping a region of the second surfaces 212, 222 of the waveguides 21, 22 that is at least in contact with the groove 30 as seen from the normal direction of the substrate surface 50A; and a non-reciprocity member 31 that is located so as to be in contact with the side surfaces 213, 223 of the waveguides 21, 22 in the groove 30.SELECTED DRAWING: Figure 1
Inventors:
SUGITA TAKEYA
GOTO TAICHI
GOTO TAICHI
Application Number:
JP2022036555A
Publication Date:
September 22, 2023
Filing Date:
March 09, 2022
Export Citation:
Assignee:
KYOCERA CORP
UNIV TOYOHASHI TECHNOLOGY
UNIV TOYOHASHI TECHNOLOGY
International Classes:
G02B27/28; G02B6/12; G02B6/125; G02B6/126; G02B6/13
Attorney, Agent or Firm:
Kenji Sugimura
Mitsutsugu Sugimura
Shin Tsubouchi
Kazushige Utsumi
Mitsutsugu Sugimura
Shin Tsubouchi
Kazushige Utsumi
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