Title:
接合方法、プログラム、コンピュータ記憶媒体、接合装置及び接合システム
Document Type and Number:
Japanese Patent JP6770832
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To appropriately join a plurality of chips arranged on a substrate to the substrate.SOLUTION: A joining method, in a state in which a wafer has a first temperature T1 inside an airtight treatment chamber, compresses the inside of the treatment chamber to a second pressure P2 higher than an atmospheric pressure (step S3); then, heats the wafer to a second temperature T2 higher than the first temperature T1 (step S4); then, joins a plurality of chips to the wafer while keeping the inside of the treatment chamber at the second pressure P2 and keeping the wafer at the second temperature T2 (step S5); then, cools the wafer to a third temperature T3 lower than the second temperature T2 (step S6); and, then, decompresses the inside of the treatment chamber to the atmospheric pressure (step S7).SELECTED DRAWING: Figure 9
Inventors:
Wakamoto Yukihiro
Chen Shunkichi
Sunil Wickrumanayaka
Basara Najendra Secar
Sherin
Chong Sir Chung
Daniel Ismael
Chen Shunkichi
Sunil Wickrumanayaka
Basara Najendra Secar
Sherin
Chong Sir Chung
Daniel Ismael
Application Number:
JP2016114300A
Publication Date:
October 21, 2020
Filing Date:
June 08, 2016
Export Citation:
Assignee:
エージェンシー フォー サイエンス，テクノロジー アンド リサーチ
東京エレクトロン株式会社
東京エレクトロン株式会社
International Classes:
H01L21/60; B23K20/00; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2010263200A | ||||
| JP2007180447A | ||||
| JP2015060902A | ||||
| JP2014096608A |
Foreign References:
| WO2011007531A1 |
Attorney, Agent or Firm:
Tetsuo Kanamoto
Koji Hagiwara
Naoki Ogita
Koji Hagiwara
Naoki Ogita