PURPOSE: To perform an accurate key input decision, by setting a reference level higher or lower than the high/low decision level of the 1st OR circuit according to whether the signal processing of two key matrix circuits is based upon negative or positive logic.
CONSTITUTION: The key matrix circuits 11 and 12 connect with respective longitudinal lines l10∼l17 and l31∼l47; a key scanning signal KS outputted by a key scanning counter 13 is supplied to a decoder 14, which supplies a step signal to each lateral lines l20∼l27 and l40∼l47 to specify lines. Then, the corresponding lateral lines l20∼l27 and l40∼l47 of the circuits 11 and 12 are coupled mutually and their outputs are sent to two-input OR gates 151∼158 forming the 1st OR circuit. Thus, key return signals R0∼R7 are obtained from gates 151∼158. For example, if the longitudinal and lateral lines l10 and l40 drop in level when a key contact K65 is made, a key return signal is outputted from the gate 151 and a comparator 161 outputs a shift signal SO.
MORIMOTO TAKAO
KURIMOTO MASAO
ENOMOTO YUKIO
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