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Title:
KEY INPUT SYSTEM
Document Type and Number:
Japanese Patent JPS62102319
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of required connection terminals as many as operation keys by providing a selecting means which selects one key input/ output line and impresses a voltage and a key switch group, and detecting said impressed voltage and discriminating an operation key.

CONSTITUTION: The control part 11 of a microprocessor 1 equipped with a CPU, etc., inputs and outputs data to and from a control buffer 12, and sends out signals of held values in registers 12aW12c to a key output latch circuit 13 which outputs the timing of key sampling and a key input latch circuit 14 which latches an actual input signal. A decoder 15, on the other hand, holds one of signal lines at H according to the input signal and is connected to a key matrix circuit M and the key input latch circuit 14 through a key output buffer 16. Then, the key input latch circuit 14 latches key operation signals inputted to input terminals K1WK12 and sends them to said control part 11, so that a key which is operated is discriminated from the signal from the circuit 14.


Inventors:
MOCHINAGA NOBUYUKI
Application Number:
JP24183785A
Publication Date:
May 12, 1987
Filing Date:
October 29, 1985
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H03M11/00; G06F3/023; H03M11/04; H03M11/22; (IPC1-7): G06F3/023; H03M11/00
Attorney, Agent or Firm:
Takehiko Suzue



 
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