Title:
積層体
Document Type and Number:
Japanese Patent JP6450456
Kind Code:
B2
Abstract:
Provided is a laminate with which excellent processability of a device wafer can be achieved, even if the circuit surface of the device wafer is covered with a moulding material, and a temporary adhesive layer is subsequently provided to the surface to bond the device wafer and a carrier substrate together. This laminate is provided with: a device wafer having a circuit surface; a moulding layer which covers the circuit surface; and a temporary adhesive layer positioned on the surface of the moulding layer. The number of voids having a maximum length of at least 30 µm when observed from a direction orthogonal to the film surface of the temporary adhesive layer using an optical microscope is not more than 3 per 700 cm2 of the film surface of the temporary adhesive layer. The arithmetic average surface roughness Ra of the temporary adhesive layer satisfies Ra ≤ 10 µm.
Inventors:
Seiya Masuda
Yoshiki Kamochi
Yoshiki Kamochi
Application Number:
JP2017514201A
Publication Date:
January 09, 2019
Filing Date:
April 22, 2016
Export Citation:
Assignee:
FUJIFILM Corporation
International Classes:
H01L21/304; H01L21/02; H01L21/56; H01L23/29; H01L23/31
Domestic Patent References:
| JP2011155191A | ||||
| JP201550268A | ||||
| JP2007311728A |
Attorney, Agent or Firm:
Patent Service Corporation Patent Office Sykes