Title:
改良された補剛材を有する積層シリコンパッケージアセンブリ
Document Type and Number:
Japanese Patent JP6728363
Kind Code:
B2
Abstract:
A chip package assembly and method for fabricating the same are provided which utilize a stiffener to improve a package substrate against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die and a stiffener. The package substrate has a first surface and a second surface coupled by a side wall. The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface bonded to at least one of the first and second surfaces of the package substrate.
Inventors:
Zofni, Nael
Rho, Shin S
Shin, Indigit
Chawaret, Raghunandan
Hari Haran, Ganesh
Rho, Shin S
Shin, Indigit
Chawaret, Raghunandan
Hari Haran, Ganesh
Application Number:
JP2018535415A
Publication Date:
July 22, 2020
Filing Date:
October 26, 2016
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2005159136A | ||||
| JP2006196857A | ||||
| JP2003100924A | ||||
| JP2010192653A | ||||
| JP2001196487A | ||||
| JP2001135937A | ||||
| JP2003068931A |
Foreign References:
| US20060220224 |
Attorney, Agent or Firm:
Fukami patent office