Title:
大面積トランスデューサ・アレイ
Document Type and Number:
Japanese Patent JP5090641
Kind Code:
B2
Abstract:
Methods of fabricating a tiled transducer array are disclosed. Embodiments of the methods include fabricating a wafer comprising a plurality of transducers, dicing the wafer to form individual transducers, testing the individual transducers to identify a plurality of known good transducers, preparing a substrate having a front side and a backside wherein the backside of the substrate comprises a plurality of connectors, positioning the plurality of known good transducers on the front side of the substrate and aligning the plurality of transducers in a horizontal direction and a vertical direction to form a transducer array, and electrically coupling the connectors on the substrate to the plurality of known good transducers, wherein the connectors are arranged such that each of the plurality of known good transducers may be electrically coupled to an electronic device disposed on the backside of the substrate, through a respective one or more of the plurality of connectors.
Inventors:
Rayet Ann Fisher
William Edward Burdick, Junior
James Wilson Rose
William Edward Burdick, Junior
James Wilson Rose
Application Number:
JP2005347492A
Publication Date:
December 05, 2012
Filing Date:
December 01, 2005
Export Citation:
Assignee:
GENERAL ELECTRIC COMPANY
International Classes:
H04R1/40; A61B8/00; G01N29/24; H04R3/00; H04R23/00; H04R31/00
Domestic Patent References:
| JP2002530145A | ||||
| JP7170600A | ||||
| JP2001198122A | ||||
| JP2002028159A | ||||
| JP6335091A | ||||
| JP2004088056A | ||||
| JP2003503923A | ||||
| JP2003180688A | ||||
| JP2004174227A | ||||
| JP2001004602A | ||||
| JP2004511290A | ||||
| JP2002027594A |
Foreign References:
| WO2003011748A1 | ||||
| WO2003101695A1 |
Attorney, Agent or Firm:
Arakawa Satoshi
Hirokazu Ogura
Toshihisa Kurokawa
Hirokazu Ogura
Toshihisa Kurokawa