大規模集積回路およびそのテスト方法

Japanese Patent JP3978464

B2

Each touchdown of a probe card during wafer-sort testing of integrated circuits can leave a gouge in the pad metal. These gouges reduce the reliability of any wire bond to that pad as voids can be left in the bond where the gouges are. A second auxiliary test pad is adjacent to the primary bonding pad. This second auxiliary test pad is electrically connected to the primary bonding pad. Thus probes can land on the second auxiliary pad rather than the primary pad. Gouges are made on the second pad rather than the primary pad. This second test pad allows for multiple probing. Multiple probing is needed for testing large embedded memories on large logic chips such as video controllers. The yield of large memories is increased by laser repair. Probing and testing is required both before and after laser repair using a memory test machine. However, a logic test machine is used to test the logic controller portion of the IC, but cannot generate the millions of test vectors needed to fully test the embedded memory. Only the pins that are used for both memory testing and logic testing need the second auxiliary pads. Thus the probes can land on the second test pads multiple times while the wire bond is made to the primary bonding pad.

JPS5862282	【考案の名称】電極ホルダ-機構
JPH1183896	WAFER PROBER AND POSITIONING METHOD
JP2574942	[Title of Invention] Electrical probe

Puerard, Deep Radius

JP50063297A

September 19, 2007

May 20, 1996

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Faust Communications Limited Liability Company

G01R1/06; H01L21/66; G01R31/28; G11C29/02; G11C29/04; G11C29/48; H01L23/58

JP4096343A
JP55128168A

Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa

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