PURPOSE: To obtain the latch circuit with low power consumption which suppresses unnecessary power consumption due to the operation of the logic circuit in an input stage when the operation frequency of an input signal is lower than the operation frequency of an enable signal.

CONSTITUTION: An exclusive OR gate 10 which compares the state of the input signal to a data input terminal 1 with the state of the output signal from an output terminal 3 is added and when the enable signal 2a varies, the output of the exclusive OR gate 10 is connected to the input terminals of three-input NAND gates 6a and 7a so that neither of the three-input NAND gates 6a and 7a operates on condition that the input signal 1a is in the same state as that before the enable signal 2a varies.