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Patent Searching and Data


Title:
LATCH CIRCUIT
Document Type and Number:
Japanese Patent JPS5711526
Kind Code:
A
Abstract:

PURPOSE: To automatically set the initial value of a circuit at power supply application to a desired logical level, by connecting a cpapcitor between an inverter input and a grounded terminal or power supply terminal.

CONSTITUTION: When a voltage at a power supply terminal 16 is raised from 0 voltage, each IG-FET is at off-state at a range lower than a threshold voltage of the IF-FET. When a V16 is further increased, since V35 V36 is expressed, a Vth6 reaches the threshold voltage of low level of an inverter 6 after time t1. Thus, the V35 increases and the output voltage of an inverter 5 decreases, then an output voltage V34 of an inverter 6 increases to "1" level rapidly, and the output voltage V36 of an inverter 5 decreases to "0" level rapidly. Thus, the initial value of the output of the latch circuit can be set to "0" level at the power supply application.


Inventors:
KOYADA HIROSHI
Application Number:
JP8630980A
Publication Date:
January 21, 1982
Filing Date:
June 25, 1980
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K3/037; H03K3/356; (IPC1-7): H03K3/037
Domestic Patent References:
JPS496379A1974-01-21
JPS54140444A1979-10-31
JPS488155U1973-01-29