LATCH-MISS DETECTING CIRCUIT AND PLL CIRCUIT

Japanese Patent JP3407604

B2

PROBLEM TO BE SOLVED: To securely detect a latch miss of a logic circuit due to an increase in operating frequency by providing a frequency-dividing circuit which stops frequency-dividing operation, when the operation becomes unstable and discriminating whether the output of the frequency dividing circuit continues to vary or to be fixed.
SOLUTION: The moment a latch miss occurs on one of flip-flops 1 and 2, a Q outputs of the flip-flops 1 and 2 turns into a same logical level and the operation as a frequency 2-divider stops at that moment. The Q output of the flip-flop 2 is divided by a frequency divider 3 to 1/N (N: arbitrary integer). The cycles of the output signal of the frequency divider 3 are 2N times as large as an operating clock fvco. The frequency division ratio N is set to such a value, that a cycle measuring instrument 4 can measure the cycles of the output signal of the frequency divider 3 with a fixed clock fxi 1. In this case, when the latch miss occurs to the flip-flop 1 or 2 and the operation as the frequency 2-divider stops, the output of the frequency divider 3 also stops and the logical level is fixed.

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Takashi Inoue
Masakazu Fujimoto

JP16083497A

May 19, 2003

June 18, 1997

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Matsushita Electric Industrial Co., Ltd

H03L7/18; H03K21/40; H03L7/08; H03L7/10; (IPC1-7): H03K21/40; H03L7/08; H03L7/10

JP7273642A

Fumio Iwahashi (2 others)

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