PURPOSE: To improve the hFE, and to enhance the frequency characteristic of a lateral transistor by a method wherein a P type collector layer on an N- type Si substrate is surrounded with an N+ type layer.

CONSTITUTION: The P type collector layer 3 is surrounded with the N+ type layer 4. Accordingly when a reverse bias is applied, a depletion layer generated from collector-base junction is nearly hard to extend to the substrate 1 of N- type base. Therefore the withstand voltage is enhance remarkably. While because the withstand voltage to be decided by avalanche breakdown is reduced, impurity concentration of the N+ type layer 4 is selected to make the punch through withstand voltage or more to be held. According to this construction, because the punch through withstand voltage between a P type emitter layer 2 and the P type collector layer 3 is enhanced sharply, base width can be narrowed. Accordingly the high hFE and the favorable frequency characteristic fT can be obtained, and the degree of freedom in regard to the circuit design is increased.