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Title:
LEVEL CONVERSION LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPS6269719
Kind Code:
A
Abstract:

PURPOSE: To obtain an interface capable of converting a level with low power consumption by connecting the one MOS transistor of a CMOS inverter circuit to the 1st power source and the other to the 2nd power source.

CONSTITUTION: A signal at 5V is inputted to an input terminal. When the signal becomes 0V from 5V, a Q11 is turned on, whereas a Q12 is turned off. Thus the output of the CMOS inverter circuit 1 comes to 5V, and a Q13 with a threshold of 1V is turned on to be conductive. The gate potentials of a Q14 and a Q15 drop, are turned on and become conductive. Since the input drops to 0V from 5V, a Q16 with a threshold of 1V is turned off and stands at a high resistance, and a power source 15V appears in the output accordingly. In the same manner, when the input becomes 5V from 1V, the Q11 and Q12 are turned off and on, respectively. Thus the output of the circuit 1 drops to 0V from 5V, and the Q13 is turned off to be high resistance. The drain of the Q14 and the gate of the Q15 become Vcc2V, and the Q14 and the Q15 are turned off to be high resistance. Since the input rises to 5V from 0V, the Q16 is turned on around 1V, and the output drops to 0V.


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Inventors:
TSUGARU KAZUNORI
SUGIMOTO YASUHIRO
Application Number:
JP20885585A
Publication Date:
March 31, 1987
Filing Date:
September 24, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K5/02; H03K19/0185; (IPC1-7): H03K19/00
Domestic Patent References:
JP59073846B
Attorney, Agent or Firm:
Noriyuki Noriyuki



 
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