LEVEL CONVERTER CIRCUIT STABILIZING OPERATION DURING POWER SUPPLY STARTUP

Title:

LEVEL CONVERTER CIRCUIT STABILIZING OPERATION DURING POWER SUPPLY STARTUP

Document Type and Number:

Japanese Patent JP3763775

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To prevent no startup of a low power supply caused by occurrence of once-through current, at node intermediate electric potential within a level converter circuit, during power supply turn-on.
SOLUTION: A level converter circuit conducts level conversion of a first signal A of a low power supply side VccL into a second signal X of a high power supply side VccH. The level converter circuit comprises first and second transistors N4 and N6 controlled by the first signal A and the opposite phase signal/A and placed at the ground side, third and fourth transistors P3 and P4 connected to the first and the second transistors N4 and N6 respectively and placed at the high power supply side and cross-connected between the gate and the drain, and an initialization circuit 20 for pulling down (or pulling up) either a first node B between the first and the third transistors or a second node/B between the second and the fourth transistors to the ground electric potential (or the high power supply electric potential) by a direct current path during startup of the high power supply.

Inventors:

Kihara Fukuji
Kaneko Yuki

Application Number:

JP2001362632A

Publication Date:

April 05, 2006

Filing Date:

November 28, 2001

Export Citation:

Click for automatic bibliography generation Help