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Patent Searching and Data


Title:
LEVEL DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS6189522
Kind Code:
A
Abstract:

PURPOSE: To facilitate adjustment, by inputting voltage obtained by rectifying the signal level of a transmission path to two comparators while inputting the outputs of the first and second comparators to the set and reset terminals of FF when the output of the first comparator reached a first predetermined value or more and that of the second one reached to a second predetermined value or less.

CONSTITUTION: The signal level of a line is rectified by a rectifier circuit 3 and the output voltage Vi of said circuit 3 is inputted to first and second comparators 7, 8 having potentiometers R3, R4 and, when the voltage Vi reached first predetermined voltage or more, one-level is outputted from the comparator 7 and, when reached second predetermined voltage or less, one-level is outputted from the comparator 8. When the voltage V1 takes the value between both predetermined voltages, a zero level is outputted from the comparators 7, 8 and the outputs of both comparators 7, 8 are respectively inputted to the set and reset terminals of FF9 and an alarm is respectively outputted and restored on the basis of one level outputs of the comparators 7, 8. By this method, adjustment can be performed alone by the potentiometers R3, R4.


Inventors:
MATSUSHITA AKIHIRO
Application Number:
JP21096984A
Publication Date:
May 07, 1986
Filing Date:
October 08, 1984
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G08B23/00; G08B25/00; G01F23/00; (IPC1-7): G01F23/00
Attorney, Agent or Firm:
Koshiro Matsuoka