LEVEL DOWN CONVERTER - 富士通株式会社

Title:

LEVEL DOWN CONVERTER

Document Type and Number:

Japanese Patent JP3910568

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a level down converter that is operable in a high frequency even if a power supply voltage is low and has little influence of character dispersion between a p channel MOS transistor and an n-channel MOS transistor.
SOLUTION: The level down converter is provided which has first inverters (101a and 102a) each of which is fed with a first power supply voltage and outputs a signal obtained by logically inverting an input signal, and second inverters (106b and 107b) each of which is fed with a second power supply voltage lower than the first power supply voltage and outputs signals obtained by logically inverting the output signals of the first inverters. Each of the first inverters includes a transistor having a gate insulated film with a first film thickness. Each of the second inverters includes a transistor having a gate insulated film with a second film thickness thinner than the first film thickness.

Inventors:

Masafumi Kondo
Toshihiko Mori

Application Number:

JP2003293568A

Publication Date:

April 25, 2007

Filing Date:

August 14, 2003

Export Citation:

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