To provide a level shifter circuit capable of preventing superposition of spike noise on an output signal and decrease in response speed.
A level shifter circuit includes: a first circuit 10 receiving an input signal A of a first potential system using a first high potential and a first low potential as a power supply potential, and outputting a first signal XA that is a signal of the first potential system; a second circuit 20 generating an output signal Y depending on the input signal, of a second potential system using a second high potential and a second low potential as a power supply potential; and a buffer circuit receiving the input signal, and generating a second signal B that is a signal of the first potential system and logically equivalent to the input signal. The second circuit includes: a first stage inverter receiving the second signal, and outputting a third signal XD; and a first stage switch switching connection and disconnection between the first stage inverter and a power supply supplying the second high potential or a power supply supplying the second low potential on the basis of the first signal. The second circuit generates the output signal on the basis of the third signal.
| JP2007180671A | 2007-07-12 | |||
| JPH01196917A | 1989-08-08 | |||
| JP2010532142A | 2010-09-30 |
Mitsue Obuchi
Misa Nagata
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