Title:
振幅制限回路
Document Type and Number:
Japanese Patent JPH065805
Kind Code:
B2
Abstract:
An amplitude limiter circuit including first and second semiconductor elements of different conductivity types having their emitters connected with each other, first and second impedance elements connected to bases of said first and second semiconductor elements, respectivly, a switch and a capacitor connecting said first and second impedance elements, a third impedance element through which continuous oscillation is fed to the emitters of said first and second semiconductor elements, and means for applying control signal to said switch to operate said switch, thereby producing damped oscillation signal which finally reduces to zero.
Inventors:
KAWASAKI MOTOAKI
Application Number:
JP16630685A
Publication Date:
January 19, 1994
Filing Date:
July 27, 1985
Export Citation:
Assignee:
CANON KK
International Classes:
H03G3/00; G11B5/012; G11B5/024; H03G3/10; H03K3/70; H03K4/94; (IPC1-7): H03G3/00; G11B5/024; H03G3/10
Attorney, Agent or Firm:
丸島 儀一
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