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Patent Searching and Data


Title:
LINE TERMINATING DEVICE AND WIRING DEVICE
Document Type and Number:
Japanese Patent JPH1065828
Kind Code:
A
Abstract:

To prevent the communication error due to the influence of line wiring or the like by providing a system with plural signal transmitting/receiving means, plural delay means for delaying I/O signals to/from respective signal transmitting/receiving means and an adding means for adding output signals from respective signal transmitting/receiving means inputted through the delay means.

A signal received by an ISDN line 2 is inputted to respective drivers 140-1 to 140-n through delay circuits 130-1 to 130-n. The signal is received by respective ISDN communication terminals 7-1 to 7-n through terminal resistors 50-1 to 50-n, the downward wiring of cables 60-1 to 60-n and terminal resistors 4-1 to 4-n. On the other hand, signals transmitted from the terminals 7-1 to 7-n are received by respective receivers 150-1 to 150-n through the terminal resistors 50-1 to 50-n, the upward wiring of the cables 60-1 to 60-n and the resistors 4-1 to 4-n. The received signals are delayed by respective delay circuits 130-1 to 130-n and inputted and processed to/by an adding circuit 120. A TTL interface type DSU 110 processes an input signal from the circuit 120 and transmits the processed signal to an ISDN circuit 2.


Inventors:
YAMADA SHINICHI
Application Number:
JP21633496A
Publication Date:
March 06, 1998
Filing Date:
August 16, 1996
Export Citation:
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Assignee:
YAMAHA CORP
International Classes:
H04L29/10; H04B3/20; H04L12/02; H04M11/00; (IPC1-7): H04M11/00; H04B3/20; H04L12/02; H04L29/10
Attorney, Agent or Firm:
Masatake Shiga (2 outside)