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Title:
Ｖ－ＮＡＮＤワード線スタック用ライナ
Document Type and Number:
Japanese Patent JP7362780
Kind Code:
B2
Abstract:
Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

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Inventors:
Wrench, Jack Lean S.
Yang, Esion
Wu, Young
Tang, Wei.
Gandicotta, Shrine Nivers
Rin, Youngjin
Bernal Ramos, Carla M.
Chen, Shi Chang
Application Number:
JP2021568856A
Publication Date:
October 17, 2023
Filing Date:
May 19, 2020
Export Citation:
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Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L21/28; H01L21/285; H01L21/3205; H01L21/336; H01L21/768; H01L23/532; H01L29/788; H01L29/792; H10B41/27
Domestic Patent References:
JP2018137388A
JP11330006A
JP2013534058A
JP2016225434A
JP2019160918A
Foreign References:
WO2019036292A1
Attorney, Agent or Firm:
Sonoda & Kobayashi Patent Attorneys Corporation



 
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