Title:
論理回路設計支援システム
Document Type and Number:
Japanese Patent JP3602697
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve quality and to attain quick processing or the like by extracting operation chains from a control data flow graph(C/DFG) generated by reading out operation description and allocating control steps to the C/DFG grouped based on the priority of the chains to synthesize a logical circuit. SOLUTION: An operation description input part 101 reads out operation description and generates a C/DFG and a restriction condition input part 102 stores a read synthesis restriction condition in a storage part 104. A priority calculation part 107 obtains priority in each sort of all operation chains satisfying a restriction condition which are extracted by an operation chain extraction part 106 and a grouping part 108 groups the C/DFG based on the priority. Then a control step allocation part 109 allocates control steps to respective nodes of the grouped C/DFG and an allocation part 103 allocates circuit elements to respective allocated nodes of the C/DFG to synthesize a logical circuit.
Inventors:
Shigeta Yoshinori
Application Number:
JP25379797A
Publication Date:
December 15, 2004
Filing Date:
September 18, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50
Domestic Patent References:
| JP8101861A |
Other References:
Marwedel, P. et al.,Built-in chaining: introducing complex components into architechtural synthesis,Proc. ASP-DAC,IEEE,1997年 1月31日,p.599-605
Attorney, Agent or Firm:
Hidekazu Miyoshi