PURPOSE: To facilitate the logic circuit design by constituting the title circuit by a 1st conduction transfer gate pair, the two end conduction type MISFETs, an inverter circuit and a 2nd conduction type MISFET whose source is connected to a power supply.

CONSTITUTION: In inputting an L level signal to both input terminals A, B, for example, N-channel MOSFETs TN101 and TN102 are nonconductive and P-channel MOSFETs TP101 and TP102 are conductive. Thus, the inner node N100 is charged to an H level through the TP101, TP102 and the level of an output terminal O goes to L by an inverter circuit comprising the TP103 and TN103. In this case, the P-channel MOSFET TP104 is conductive. Thus, an exclusive OR circuit or its inverting output circuit where no current path exists between the input and output terminals and the load capacitance when viewed from the input terminal is independent of the load capacitance connected to the output terminal is obtained and the estimate of the load capacitance or delay time is facilitated.